1. Technical Field
This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. More particularly, this disclosure relates to a semiconductor device having a switching function and a method of manufacturing the semiconductor device.
2. Description of the Related Art
FIGS. 1, 2, 4, 6, 8, 10 and 12 are plan views illustrating a conventional method of manufacturing a transistor. FIGS. 3, 5, 7, 9, 11 and 13 are cross-sectional views taken along I-I′ lines in FIGS. 2, 4, 6, 8, 10 and 12, respectively.
Referring to FIG. 1, dummy regions 11 and active regions 12 are formed at an upper portion of a semiconductor substrate 10. The dummy regions 11 are arranged in a first direction. However, the dummy regions 11 are not connected to one another in the first direction.
Thereafter, a silicon oxide layer (not shown) is formed on the semiconductor substrate 10 to cover the dummy regions 11 and the active regions 12. A planarization process is then performed on the silicon oxide layer until the dummy regions 11 and the active regions 12 are exposed. Thus, an isolation layer pattern 30 is formed.
The dummy regions 11 may prevent the active regions 12 from easily leaning while the planarization process is performed. However, when the sizes of the dummy regions 11 are relatively small, the dummy regions 11 as well as the active regions 12 may lean while the planarization process is performed.
The isolation layer pattern 30 extends in a second direction substantially perpendicular to the first direction between the dummy regions 11. Thus, the dummy regions 11 are electrically insulated from one another by the isolation layer pattern 30.
Referring to FIGS. 2 and 3, a mask structure 40 is formed on the dummy regions 11, the active regions 12 and the isolation layer pattern 30. The mask structure 40 has first openings 5c partially exposing the dummy regions 11, the active regions 12 and the isolation layer pattern 30. The first openings 5c and the mask structure 40 extend in the second direction. The mask structure 40 includes silicon nitride layer patterns 42 and buffer layer patterns 41. The nitride layer patterns 42 are formed on each of the buffer layer patterns 41.
Thereafter, the dummy regions 11 and the active regions 12 are etched using the mask structure 40 as an etch mask. Thus, first grooves 1c and second grooves (not shown) are formed at upper portions of the dummy regions 11 and upper portions of the active regions 12, respectively. Because the first openings 5c extend in the second direction, the first grooves 1c and the second grooves also extend in the second direction.
As described above, the isolation layer pattern 30 exists between the dummy regions 11. The isolation layer pattern 30 may be minimally etched while the dummy regions 11 and the active regions 12 are etched to form the first grooves 1c and the second grooves. Thus, the sections of the first grooves 1c taken along the line I-I′ are substantially asymmetric.
Referring to FIGS. 4 and 5, a silicon oxide layer 50 having a substantially uniform thickness is formed on the mask structure 40, the dummy regions 11, the active regions 12 and the isolation layer pattern 30. Thus, inner faces of the first grooves 1c and the second grooves are covered with the silicon oxide layer 50. Here, the silicon oxide layer 50 may conform to the first grooves 1c and the second grooves.
Referring to FIGS. 6 and 7, an anisotropic etching process is performed on the silicon oxide layer 50 so that portions of the silicon oxide layer 50, the portions being located on bottom faces of the first grooves 1c, bottom faces of the second grooves, the mask structure 40 and the isolation layer pattern 30, may be selectively removed. Thus, silicon oxide layer patterns 51 are formed on sidewalls of the first grooves 1c and the second grooves.
Thereafter, portions of the dummy regions 11 and portions of the active regions 12 that are exposed through the first grooves 1c and the second grooves, respectively, are isotropically etched using the mask structure 40 and the silicon oxide layer patterns 51 together as an etch mask. Thus, third grooves 3c communicated with the first grooves 1c are formed under the first grooves 1c. The third grooves 3c extend in the second direction. In addition, fourth grooves (not shown) communicated with the second grooves are formed under the second grooves. The fourth grooves also extend in the second direction.
As illustrated in FIG. 7, the isolation layer pattern 30 is formed between the dummy regions 11. Thus, the sections of the third grooves 3c taken along the first direction are not substantially circular shapes even though the third grooves 3c are formed by an isotropic etching process. That is, the sections of the third grooves 3c taken along the first direction are substantially asymmetric.
Referring to FIGS. 8 and 9, the mask structure 40 and the silicon oxide layer patterns 51 are removed. Thereafter, a gate oxide layer 60 including silicon oxide is formed on faces of the active regions 12 and the dummy regions 11, the faces being exposed by the isolation layer pattern 30. The gate oxide layer 60 has a substantially uniform thickness. Thus, inner faces of the first grooves 1c, the second grooves, the third grooves 3c and the fourth grooves are covered with the gate oxide layer 60.
Thereafter, a gate electrode layer 70 including a first portion 70a and second portions 70b is formed on the gate oxide layer 60 and the isolation layer pattern 30. The first portion 70a fills the first grooves 1c and the second grooves that have been partially filled with the gate oxide layer 60. The second portions 70b fill the third grooves 3c and fourth grooves that have been partially filled with the gate oxide layer 60. The second portions 70b have voids 5d. 
As described above, the sections of the third grooves 3c taken along the first direction are not substantially circular shapes. Thus, the voids 5d generated in the second portions 70b while the gate electrode layer 70 fills up the third grooves 3c may easily migrate from the centers of the second portions 70b. That is, a void migration may be generated so that failure of a semiconductor device may occur.
Gate mask layer patterns 80 are formed on the gate electrode layer 70. Second openings 6c are defined between the gate mask layer patterns 80. The gate electrode layer 70 is partially exposed through the second openings 6c. The second openings 6c and the gate mask layer patterns 80 extend in the second direction. Here, the gate mask layer patterns 80 correspond to word lines.
Referring to FIGS. 10 and 11, the gate electrode layer 70 and the gate oxide layers 60 are subsequently etched using the gate mask layer patterns 80 as an etch mask. Thus, gate electrodes 71 and gate oxide layer patterns 61 are formed.
Two gate electrodes 71 are formed on each of the active regions 12. In addition, as illustrated in FIG. 11, two gate electrodes 71 are also formed on each of the dummy patterns 11. This is because the dummy regions 11 are separated from one another.
Dummy impurity regions 13 and active impurity regions 14 are formed at upper face portions of the dummy regions 11 and upper face portions of the active regions 12, respectively, by using the gate mask layer patterns 80 and the isolation layer pattern 30 together as an ion implantation mask.
Referring to FIGS. 12 and 13, an insulating layer (not shown) is formed to cover the dummy impurity regions 13, the active impurity regions 14, the isolation layer pattern 30, the gate oxide layer patterns 61, the gate electrodes 71 and the gate mask layer patterns 80.
Thereafter, the insulating layer is anisotropically etched to form spacers 90 on sidewalls of the gate mask layer patterns 80, the gate electrodes 71 and the gate oxide layer patterns 61. Thus, a semiconductor device including the dummy impurity regions 13, the active impurity regions 14, the gate oxide layer patterns 61, the gate electrodes 71, the gate mask layer patterns 80 and the spacers 90 may be fabricated.
As described above, the dummy regions 11 are spaced apart from one another in the first direction. Thus, if the dummy regions 11 are relatively small, the dummy regions 11 may lean or collapse.
In addition, because the isolation layer pattern 30 is formed between the dummy regions 11, the sections of the third grooves 3c taken in the first direction may not be substantially circular shapes even though the third grooves 3c are formed by the isotropic etching process. That is, the sections of the third grooves 3c taken in the first direction may be substantially asymmetric.
Thus, the voids 5d generated in the second portions 70b may easily migrate from the centers of the second portions 70b while the gate electrode layer 70 fills the third grooves 3c. As a result, the voids 5d may cause the failure of a semiconductor device.